Signal processing apparatus and method, and data recording/reproducing apparatus using the same

ABSTRACT

A signal processing apparatus capable of reducing burst error generation, and a highly reliable data recording/reproducing apparatus using this signal processing apparatus. This signal processing apparatus has a simple error detection/correction circuit provided just before a modulated code demodulator, thereby correcting error of a pattern easy to occur in a maximum likelihood decoder. The simple error detection/correction circuit is an error detection/correction circuit using a linear error correction code, for example, an error correction code (CRCC) formed of a cyclic code. Thus the number of burst errors after the modulated code demodulator can be decreased.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a signal processing apparatusand method capable of suppressing the generation of burst error, and toa data recording/reproducing apparatus using the same.

[0003] 2. Description of Related Art

[0004] The magnetic disk recorder represented as a datarecording/reproducing apparatus has been more and more requested to havea capability of higher recording density, and the signal processingtechnology in the recording/reproducing system for supporting thisrequest has also been developed toward the higher recording densitycapability.

[0005] In order to cope with the S/N ratio reduced by the intersymbolinterference associated with high density recording, a partial responseequalization system has been employed. For example, PRML (PartialResponse with Maximum Likelihood detection) class 4 has been used todetect a signal sequence nearest to a reproduced signal by means of aknown interference caused in a reproducing channel, and it is alreadyutilized in the magnetic disk recorder.

[0006]FIG. 1 shows a flow of digital information reading processing inthe conventional EEPRML (Extended Extended PRML). A signal 1 read from ahead is equalized by a PR equalizer 2 into a signal 3. Then a decodeddata sequence 5 that was actually recorded is estimated from the signal3 by a maximum likelihood decoder 4. The estimated coded sequence 5 issupplied through a postcoder 6 to a 16/17 code demodulator 10, where itis decoded into an information data sequence 11. The information datasequence 11 undergoes error detection and correction in a Reed-Solomondecoder 12.

[0007] The most of the error sequences in the maximum likelihood decoder4 have a short distance from a correct sequence. The error sequenceswith shorter distances from the correct sequence are examined by use ofan error low graph.

[0008]FIG. 2 is a schematic graph of error flow within a distance of 8from the correct sequence in EEPRML. In each state (e_(t-3) e_(t-2)e_(t-1) e_(t)), e_(t) represents error at time t. When e_(t) is 0, thecorresponding bit has no error. Similarly when e_(t) is respectively +and −, the corresponding bits “0” and “1” have errors of “1” and “0”,respectively. The numbers attached on the arrows in the flow diagramindicate the distance from the correct sequence that increase with thetransition of the corresponding errors. From FIG. 2, it will beunderstood that the error sequences from the maximum likelihood decoder4 in EEPRML have errors of ± (+−+) (three consecutive errors), ± (+−+− .. . ) (four or more consecutive errors), and ± (+−+00+−+) in the orderof shorter distance from the correct sequence. The frequency of actualerror occurrence is affected not only by the distance from the correctsequence but by the mutual correlation between the error length andnoise. The actual error is likely to occur in order of errors of threeconsecutive bits, one bit, two bits, five bits and four bits. Where, theerror of four consecutive bits “0101 . . . ” is represented as “1010 . .. ” or vice versa.

[0009] Also by use of more advanced PRML or by slightly movingcoefficients of partial response the frequency order is somewhatchanged, but error tendency is not changed.

[0010] The short errors on the modulated codes in the maximum likelihooddecoder 4 are expanded into burst error by the demodulator 10. If, forexample, 16/17 modulation code is used, the worst expansion is 4 bytes.This corresponds to the worst value in the case where errors occur atthe final bit of 16/17 code and are propagated to the next code word bythe postcoder 6. This error expansion causes the correction ability ofReed-Solomon code to be reduced.

SUMMARY OF THE INVENTION

[0011] Accordingly, it is an object of the invention to realize a signalprocessing apparatus and method capable of reducing burst error to asmall value, and provide a highly reliable data recording/reproducingapparatus using the same.

[0012] In order to achieve the above object, a signal processingapparatus according to the invention has a simple errordetection/correction circuit provided just before the modulated codedemodulator. The simple error detection/correction circuit can be anerror detection/correction circuit using a linear error correction code,for example, an error detection/correction circuit using an errorcorrection code (CRCC) constructed by a cyclic code.

[0013] Moreover, data reproducing means of a data recording/reproducingapparatus is constructed by using this signal processing apparatus.

[0014] Since some error patterns, that are easy to occur in the maximumlikelihood decoder, can be corrected before the modulated codedemodulator by constructing the signal processing apparatus as mentionedabove, the burst error after the demodulator can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a block diagram of a conventional signal processingapparatus;

[0016]FIG. 2 is a graph showing the change of correct and error statesin the maximum likelihood decoding of EEPRML;

[0017]FIG. 3 is a block diagram of a signal processing apparatusconcerning one embodiment of the invention;

[0018]FIG. 4 is a diagram showing a conception of linear errorcorrection used in the invention;

[0019]FIG. 5 is a circuit diagram showing an example of the errordetector used in the invention;

[0020]FIG. 6 is a diagram showing the condition in which error bits areexpanded;

[0021]FIG. 7 is a list showing a guide for generating redundant bits inthe invention;

[0022]FIG. 8 is a diagram showing redundant bits suitable for use in theinvention;

[0023]FIG. 9 is a flowchart showing algorithm for error checking andcorrection by CRCC in the invention;

[0024]FIG. 10 is a block diagram showing an arrangement for suppressingtwo event error correction;

[0025]FIG. 11 is a block diagram of a signal processing apparatusconcerning another embodiment of the invention; and

[0026]FIG. 12 is a diagram of a data recording/reproducing apparatusconcerning one embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Embodiments of a signal processing apparatus and method of theinvention will be described with reference to the accompanying drawings.Although the invention can be used in all digital signal transmissionsystems, a description will be made of data recording/reproducingapparatus, particularly a magnetic recording/reproducing apparatus usinga partial response system in the following embodiments.

[0028]FIG. 3 is a block diagram of a signal processing apparatus used inthe reproducing system of this data recording/reproducing apparatus.

[0029] Referring to FIG. 3, a recording/reproducing circuit 20 amplifiesa reproduced signal read from a recording medium by a magnetic head, andthe amplified signal 1 is equalized by the PR equalizer 2.

[0030] Then, the coded data sequence that was actually recorded isestimated by the maximum likelihood decoder 4 from the signal 3 afterthe equalization.

[0031] The estimated coded data sequence 5, which has a transmissioncharacteristic “1+D” in the magnetic recording/reproducing system, isfurther decoded to have a characteristic “1−D²” by the postcoder 6having a transmission characteristic “1−D”. Here, a symbol “D” indicatesone-bit delay. In this case, the transmission characteristic of theprecoder in the recording system needs to be “1/(1−D²)”, and thus thetotal transmission characteristic in the recording and reproducingsystems is “1”. The transmission characteristic “1−D²” is represented by“1⊕D²” when expressed using a symbol “⊕” that indicates addition inmodulo-2 computation. This transmission characteristic can be achievedby use of a delay circuit of two bits and one addition circuit.

[0032] The coded data sequence output from the postcoder 6 is processedby an error detection/correction circuit 8 using CRCC so that a shorterror pattern easy to occur in the maximum likelihood decoder 4 isdetected and corrected. The error detection/correction circuit 8 makeserror detection and correction using a linear error correction codeadded in the recording system. Thus the number of burst error to beexpanded by the 16/17 code demodulator 10 can be reduced by this simpleerror correction.

[0033] Next, the decoded data sequence 9 output from the errordetection/correction circuit 8 is demodulated by the 16/17 codedemodulator 10 into the information data sequence 11 associatedtherewith. While in this embodiment the 16/17 modulation is used asdigital modulation in order to limit the run length, another digitalmodulation method may be utilized in the invention.

[0034] Finally, the Reed-Solomon decoder 12 detects and corrects errorof the information data sequence 11.

[0035] The principle of the operation of the error detection/correctioncircuit 8 using CRCC will be described in detail. The errordetection/correction circuit 8 makes error detection/correction using alinear error correction code as described previously.

[0036] The linear error correction code is such an error detection codethat if there is error to be corrected the error can be definitely foundfrom the parity value (hereinafter, referred to as error syndrome). Asshown in FIG. 4, if “f” represents a mapping from an error polynomial toan error syndrome, and “E₀” represents the set of all polynomials forerrors to be corrected, then “f|E₀” (a mapping “f” whose domain ofdefinition is restricted to “E₀”) is injective, and the error polynomialincluded in “E₀” and the error syndrome have one-to-one correspondence.As the error detection code, a cyclic code can be used which makes iteasy to make circuits. When the cyclic code is used, the mapping “f”corresponds to the operation for finding the remainder after dividingthe error polynomial by a generator polynomial of the cyclic code.Actually, the error syndrome is calculated by, for example, an errordetector 501 shown in FIG. 5.

[0037] The algorithm for error correction is performed according to aknown burst error correction method using a cyclic code, that is,so-called trap decoding method. According to this method, if x^(c)≡1(mod g(x)) is satisfied, or if the remainder after dividing x^(c), wherec is an integer, by the generator polynomial g(x) is 1, an error patternappears by the repetition of the operation of taking the remainder leftafter multiplying the error syndrome by x and dividing the product byg(x). Thus g(x) is necessary to have no factor of x.

[0038] The error correction code formed of a cyclic code is hereinaftercalled as CRCC (Cyclic Redundance Check Code).

[0039] The structure of CRCC will be described below. Since f|E₀ isinjective, a number q of the redundant bits of cyclic code and a number#E₀ of factors in E₀ satisfy the following inequality: $\begin{matrix}{2^{q} \geqq {\# E_{0}}} & (1)\end{matrix}$

[0040] The redundant bit number q is determined from the expression (1).In order to make q as small as possible, or to suppress a number of theerror polynomials used in the error correction to a necessary minimum,it is required that CRCC be constructed so as to correct errors onlywhen a high-frequency occurrence error occurs in one CRCC coded block orover two CRCC coded blocks.

[0041] It should be noted that the error pattern to be actuallycorrected is presented after the error generated in the maximumlikelihood decoder 4 is passed through the postcoder 6 as illustrated inFIG. 3. In addition, when the error occurs over two CRCC coded blocks,the error pattern corresponds to a part of the generated error.

[0042] However, if the error detector 501 shown in FIG. 5 simply addscalculated redundant bits of cyclic code to data blocks which areobtained by dividing a modulated and coded bit sequence at a constantlength of k bits, the 0-consecutive length limited in the modulated codeis excessively broken at the added portion. This is because all theredundant bits may be “0” since the redundant bits of cyclic code arethe remainder.

[0043] Thus the 0-consecutive length limiting bits of p-q bits arecalculated from the redundant bits corresponding to the k bits of datablock where p (>q) is the number of added redundant bits. The redundantbits of cyclic code are corrected by using the 0-consecutive lengthlimiting bits, thus leading to the limit to the 0-consecutive length. Inthis case, a set of the 0-consecutive length limiting bits and theredundant bits of cyclic code after being updated forms redundant bitsof coded block of CRCC. The correction of the redundant bits isperformed so as to meet the 0-consecutive length limitation conditionand so that the sequence of data blocks of k bits with added redundantbits becomes a cyclic code word having generator polynomial g(x). Evenif the 0-consecutive length limiting bits lie on the more significantbit side or less significant bit side, this correction of redundant bitscan be performed substantially in the same procedure.

[0044] For example, p redundant bits including 0-consecutive lengthlimiting bits are added to each 16/17 (0, 6/6) modulated code 32 codewords (k=17×32=544) to form a CRCC of a code length of 544+p, and thisCRCC is combined with EEPRML. Where “0” in parentheses indicates0-consecutive, and “6/6” in the parentheses the actual consecutivelength and interleaved run length. When an error pattern is expressed,“e” represents error, and “o” no error.

[0045] The transmission characteristic of the precoder in the recordingsystem is 1/(1⊕D²), and the transmission characteristic of thereproducing system including the postcoder is 1⊕D².

[0046] The 0-consecutive length limiting bits are placed on the moresignificant bit side of the redundant bits.

[0047] It was found that consecutive 1˜5 bit errors occupy higher ranksin the occurrence frequencies of error from the maximum likelihooddecoder 4 of EEPRML. Therefore, the error pattern being corrected shouldbe a pattern of eoe, eeee, eeoee, eeooee, eeoooee after the post coder6, and a pattern appearing when these occur across the coded blocks ofCRCC. E₀ represents the set of all error polynomials representing thestate in which one of these patterns appears in one coded block of CRCC,as expressed by the following equation: $\begin{matrix}{E_{0} = {\left\{ {\left. {x^{m} \times \left( {x^{2} + 1} \right)} \middle| {m \geq 0} \right.,{{m + 2} < {544 + p}}} \right\}\bigcup\left\{ {1,x,x^{543 + p},x^{542 + p}} \right\}\bigcup\left\{ {\left. {x^{m} \times \left( {x^{3} + x^{2} + x + 1} \right)} \middle| {m \geq 0} \right.,{{m + 3} < {544 + p}}} \right\}\bigcup\left\{ {{x + 1},{x^{2} + x + 1},{x^{542 + p}\left( {x + 1} \right)},{x^{541 + p}\left( {x^{2} + x + 1} \right)}} \right\}\bigcup\left\{ {\left. {x^{m} \times \left( {x^{4} + x^{3} + x + 1} \right)} \middle| {m \geq 0} \right.,{{m + 4} < {544 + p}}} \right\}\bigcup\left\{ {{x^{2} + x},{x^{3} + x^{2} + 1},{x^{541 + p}\left( {x + 1} \right)},{x^{540 + p}\left( {x^{3} + x + 1} \right)}} \right\}\bigcup\left\{ {\left. {x^{m} \times \left( {x^{5} + x^{4} + x + 1} \right)} \middle| {m \geq 0} \right.,{{m + 5} < {544 + p}}} \right\}\bigcup\left\{ {{x^{3} + x^{2}},{x^{4} + x^{3} + 1},{x^{540 + p}\left( {x + 1} \right)},{x^{539 + p}\left( {x^{4} + x + 1} \right)}} \right\}\bigcup\left\{ {\left. {x^{m} \times \left( {x^{6} + x^{5} + x + 1} \right)} \middle| {m \geq 0} \right.,{{m + 6} < {544 + p}}} \right\}\bigcup\left\{ {{x^{4} + x^{3}},{x^{5} + x^{4} + 1},{x^{539 + p}\left( {x + 1} \right)},{x^{538 + p}\left( {x^{5} + x + 1} \right)}} \right\}}} & (2)\end{matrix}$

[0048] Miscorrection may be caused when error is corrected. Themiscorrection means the phenomenon in which additional error occurs atanother position as a result of correction operation when an errorsyndrome corresponding to an error not to be corrected coincides withthat corresponding to another error to be corrected.

[0049] Therefore, an error polynomial should be selected not to easilycause the erroneous correction in view of probability. Concretely, theset of all error polynomials E₁ is determined which is easy to occurnext to E₀. It is assumed that the miscorrection is not likely to occurin the case where an error syndrome of an element of E₁ does notcoincide with any one of the error syndromes of E₀ elements or in thecase where there is little problem even if the coincidence therebetweenoccurs.

[0050] The maximum likelihood decoder 4 considers next easy-to-occurpatterns in addition to consecutive 1˜5 bit error, that is, errors ofconsecutive 6 bits or more as shorter length patterns of the remainingerror patterns, and patterns up to eeeooeee corresponding to ±(+−+00+−+). This pattern corresponds to an error pattern having distance8 and not included in E₀.

[0051] The 0-consecutive length limiting condition of the 0-consecutivelength limiting bits, the redundant bits of cyclic code and other bitsplaced before and after those bits should be made the same (0, 6/6) as16/17 modulated code. In this case, from FIG. 6 it will be understoodthat when a sequence of bits 10000001 is fed to the precoder, aconsecutive error (distance 8) in a form of ± (+−+− . . . ) includingthe maximum error length of 8 can occur at the output. In other words,the consecutive error length supposed in E₁ should be considered up tothe maximum length of 8.

[0052] Therefore, E₁ should be determined so that E₀∪E₁ includes all of(i) patterns resulting from passing consecutive error of up to a lengthof 8 through the postcoder 6, (ii) pattern eeoeeeeoee resulting frompassing a pattern eeeooeee through the postcoder 6 and (iii) patternsappearing when those patterns (i) and (ii) is divided into plurality ofcoded blocks of CRCC.

[0053] The conditions of the redundant bits will be described below.Since 2¹²<#E₀<2¹³, it will be satisfactory if the redundant bit number pis selected to be the length 17 in the 16/17 modulated code. Thus, thecode length is 561 (=17×32+17) bits.

[0054] When p=17, the number of 0-consecutive length limiting bits s=p−qcannot be reduced to 2 or below. That is, however the polynomial ofdegree (17−s) is selected as a generator polynomial, there are suchredundant bits of cyclic code that 0-consecutive length limiting bitscannot be taken to satisfy the 0-consecutive length limit (0, 6/6).Thus, the 0-consecutive length limiting bit number is selected to be 3,and the redundant bit number q of cyclic code to be 14.

[0055] The length of the complete cyclic code having redundant bitnumber of 14 is 2¹⁴−1. An example of generator polynomial is a primitivepolynomial having the maximum code length. In this case, the obtainedcode corresponds to the length reduction of the complete cyclic code oflength 2¹⁴−1 to 561 bits. Before the trap decoding method is executed,idling is necessary by omitting to check the error pattern by the numberof times corresponding to the bit length of discarded error syndrome.

[0056] However, when bits are simply shifted by the number of timescorresponding to the bit length which the error detector 501 discarded,delay time is increased. Thus, the error syndrome is regarded as avector with basis x¹³, . . . , x, 1, and the vector of the errorsyndrome is multiplied by a fixed square matrix, thereby making theoperation for the updating of the number of times corresponding to thediscarded bit length. This type of operation will have an effect ofpreventing the delay time from being objectionable to the user unlessthe degree of the matrix or vector becomes so large.

[0057]FIG. 7 is a table showing the primitive generator polynomials ofdegree 14 capable of correcting errors belonging to E₀ that occurred inthe maximum likelihood decoder 4 and causing no miscorrection underconsecutive 6 bit error, and existence of miscorrection for errorsbelonging to E₁. The generator polynomial g(x)=g₁₄x¹⁴+g₁₃x¹³+ . . . . .. +g₂x²+g₁x+g₀ (g_(i)=0 or 1, but g₀=g₁₄=1) is expressed in hexadecimalnotation of g₁₄2¹⁴+g₁₃2¹³+ . . . . . . +g₂2²+g₁2+g₀. In addition, whenthe increased error due to erroneous correction is included in theredundant bits of CRCC, the redundant bits are removed, thus the sameresult is obtained as when the errors are left alone. Therefore, thissituation is not regarded as erroneous correction. From the results ofFIG. 7, it will be seen that even if the error pattern in the maximumlikelihood decoder 4 is an consecutive error of 8-bits or less, oreeeooeee, the generator polynomial causing no erroneous correction isonly 0×(hexadecimal notation) 72CD.

[0058] The following description is about one example of the computationof redundant bits of CRCC in the generator polynomial 0×72CD. FIG. 8shows the format of redundant bits in the following description.

[0059] (a) The redundant bits of cyclic code corresponding to 16/17 code32 code words are calculated by the error detector 501.

[0060] (b) If the redundant bits calculated at (a) are represented byc₁₃, c₁₂, . . . , c₂, c₁, c₀, the 0-consecutive length limiting bits(s₂, s₁, s₀) are expressed by the equations (3), (4) and (5).

s_(t)=1  (3) $\begin{matrix}{s_{i} = {\overset{\_}{c_{12\quad}}\quad \overset{\_}{c_{11\quad}}c_{10}\overset{\_}{c_{5}}{c_{4}\bigvee\overset{\_}{c_{13}}}\quad \overset{\_}{c_{11}}{c_{4}\bigvee\overset{\_}{c_{13}}}\quad c_{11}{\overset{\_}{c_{4}}\bigvee c_{13}}\overset{\_}{c_{12}}c_{11}{c_{4}\bigvee\overset{\_}{c_{13}}}\quad \overset{\_}{c_{12}}c_{11}\overset{\_}{c_{6}}{c_{4}\bigvee\overset{\_}{c_{13}}}c_{12}\overset{\_}{c_{11}}\quad {\overset{\_}{c_{6}}\bigvee c_{13}}\overset{\_}{c_{12}}\quad {\overset{\_}{c_{6}}\bigvee\overset{\_}{c_{13}}}c_{12}c_{11}c_{6}{\overset{\_}{c_{3}}\bigvee c_{13}}\overset{\_}{c_{12}}c_{6}{c_{3}\bigvee c_{13}}\overset{\_}{c_{12}}c_{10}{\overset{\_}{c_{3}}\bigvee\overset{\_}{c_{13}}}c_{12}c_{11}\overset{\_}{c_{10}}{c_{3}\bigvee c_{13}}\overset{\_}{c_{11}}\quad \overset{\_}{c_{4}}{c_{3}\bigvee c_{13}}c_{12}\overset{\_}{c_{11}}\quad \overset{\_}{c_{10}}\overset{\_}{c_{3}}\quad {\overset{\_}{c_{0}}\bigvee c_{13}}c_{12}c_{11}\overset{\_}{c_{10}}c_{6}\overset{\_}{c_{3}}\quad {\overset{\_}{c_{0}}\bigvee c_{13}}\overset{\_}{c_{12}}\quad \overset{\_}{c_{11}}c_{6}{\overset{\_}{c_{1}}\bigvee c_{13}}c_{12}\overset{\_}{c_{11}}c_{6}\overset{\_}{c_{3}}c_{1}{c_{0}\bigvee c_{13}}c_{12}c_{11}c_{5}c_{1}{c_{0}\bigvee\overset{\_}{c_{12}}}c_{11}\overset{\_}{c_{5}}\quad \overset{\_}{c_{1}}{c_{0}\bigvee\overset{\_}{c_{13}}}c_{12}{c_{5}\bigvee\overset{\_}{c_{12}}}\quad \overset{\_}{c_{5}}c_{4}\overset{\_}{c_{1}}\quad \overset{\_}{c_{0}}}} & (4) \\{s_{0} = {\overset{\_}{c_{12}}\quad \overset{\_}{c_{11}}\quad \overset{\_}{\quad c_{10}}c_{6}\overset{\_}{c_{3}}\quad {\overset{\_}{c_{0}}\bigvee c_{13}}c_{12}\overset{\_}{c_{11}}\quad \overset{\_}{c_{10}}\quad \overset{\_}{c_{3}}\quad {\overset{\_}{c_{0}}\bigvee\overset{\_}{c_{13}}}c_{12}c_{11}\overset{\_}{c_{10}}{c_{3}\bigvee c_{13}}\overset{\_}{c_{12}}c_{11}c_{10}{\overset{\_}{c_{3}}\bigvee c_{13}}c_{12}\overset{\_}{c_{11}}\quad \overset{\_}{c_{10}}{c_{3}\bigvee c_{13}}\overset{\_}{c_{12}}\quad \overset{\_}{c_{11}}c_{6}{c_{3}\bigvee c_{13}}c_{12}c_{11}c_{10}{\overset{\_}{c_{3}}\bigvee c_{13}}c_{11}{\overset{\_}{c_{6}}\bigvee c_{13}}\overset{\_}{c_{11}}c_{6}{\overset{\_}{c_{1}}\bigvee c_{13}}c_{12}c_{11}c_{6}c_{1}{c_{0}\bigvee\overset{\_}{c_{13}}}\quad \overset{\_}{c_{11}}{c_{4}\bigvee\overset{\_}{c_{13}}}\quad c_{11}{\overset{\_}{c_{4}}\bigvee c_{13}}\overset{\_}{c_{11}}\quad \overset{\_}{c_{4}}{c_{3}\bigvee c_{13}}\overset{\_}{c_{12}}c_{11}{c_{4}\bigvee\overset{\_}{c_{13}}}\quad \overset{\_}{c_{12}}\quad \overset{\_}{c_{11}}c_{10}{c_{5}\bigvee c_{13}}c_{12}c_{11}c_{10}\overset{\_}{c_{5}}}} & (5)\end{matrix}$

[0061] where the upper lines indicate the inversion of “0” and “1”, andv the logic sum (OR).

[0062] (c) The 0-consecutive length limiting bits (s₂, s₁, s₀) are fedto the input of the error detector in the order of s₂, s₁, s₀, and thedetector calculates the remaining redundant bits c₁₃, c₁₂, . . . , c₂,c₁, c₀ to be added after the 0-consecutive length limiting bits.

[0063] It can be confirmed that the 0-consecutive length limiting bitssatisfy the 0-consecutive length limitation of (0, 6/6) before and afterthe redundant bits of CRCC.

[0064] If the equations (3), (4) and (5) are properly rearranged, and(s₂x²+s₁x+s₀)g(x) is added to c₁₃, c₁₂, . . . , c₂, c₁, c₀, the0-consecutive length limiting bits can be placed on the less significantbit side of the redundant bits.

[0065] The correction algorithm in CRCC constructed as above will bedescribed with reference to FIG. 9. In the computation of polynomial,since “mod g(x)” is too long, and g(x) is a primitive polynomial, thecoset of F₂[x] (the set of all polynomials having an element of a fieldconsisting of 0 and 1 as coefficients and x as indeterminate element) byg(x) is regarded as an element of Galois field, and the indeterminateelement x of the remainder is represented by β. The operation ofmultiplying an error syndrome by β corresponds to shifting of errorsyndrome by supplying bit “0” to the input of error detector 501. Thenumbers attached to “Step” in the following description correspond tothose shown in. FIG. 9.

[0066] Step 901: Calculating error syndrome r(β) in the coded block 561bits of CRCC by the error detector 501.

[0067] Step 902: Detecting errors. If r(β)=0, no error is assumed, andthen at step 911 the correct information is set.

[0068] Step 903: Idling process. r(β) is multiplied by constantβ⁽¹⁶³⁸⁴⁻¹⁾⁻⁽ 561−14), thus updated, where 16384=2¹⁴. This operation canbe expressed by a matrix acting on a vector space with (β¹³, . . . ,β, 1) as a base. There is no need to multiply (β¹⁴−1)−(561−14) times byβ.

[0069] Step 904: Deciding whether r(β) takes any one of patterns beingcorrected on the basis of vector value with β¹³, . . . , β, 1 as basis.If the decision is yes, the error event is determined by r(β), and errorposition by the number of times of shifting r(β) (Step 910). In thiscase, since error pattern and error position are found, error can becorrected.

[0070] Step 905: Deciding whether the correction is possible (Step 910)or impossible (Step 909) on the basis of the matching with errorposition, because error events (attached with *) occurring over two codewords are positioned at around the most significant bit or leastsignificant bit of the coded block.

[0071] Step 906: Multiplying r(β) by β to shift r(β) when r(β) is not avalue corresponding to the error pattern being corrected.

[0072] Step 907: Deciding whether the number of times of shifting islarger than 561. If it is larger than that, since error other than theerror to be corrected occurs, the program goes to Step 909 where correctinformation is set.

[0073] Step 908: Correcting error if possible. Then, the redundant bitsof CRCC are removed.

[0074] In this embodiment, the error to be corrected is one event withinthe coded block. The error of two events occurring within the codedblock has something to cause erroneous correction. FIG. 10 is a blockdiagram of one example of the arrangement for suppressing the erroneouscorrection due to two-event error. A likelihood information 14 obtainedfrom the maximum likelihood decoder 4 is supplied to a likelihooddecider 15, which then estimates occurrence of error events. When thelikelihood decider 15 decides that an error event has occurred, thecontent of a counter 16 is incremented by one. A threshold discriminator17 determines whether or not two or more error events occur within thecoded block, and selects the operation of a CRCC decoder 8 on/off on thebasis of the decided result.

[0075] An embodiment of a signal processing apparatus and method used inthe recording system of the data recording/reproducing apparatus will bedescribed with reference to the related drawings.

[0076]FIG. 11 is a block diagram of the signal processing apparatus usedin the recording system.

[0077] First, a Reed-Solomon encoder 21 continuously generates datablocks from the input information data sequence, and adds a Reed-Solomonerror correction code to each data block.

[0078] Then, a 16/17 code modulator 23 modulates the data produced fromthe encoder 21 to produce a coded data sequence associated therewith.While in this embodiment 16/17 modulation is used as digital modulationin order to limit the run length, other digital modulation methods maybe employed in the present invention.

[0079] In addition, a CRCC encoder 25 adds redundant bits to the codeddata sequence output from the 16/17 code modulator 23. It is desiredthat the redundant bits include at least one limit bit for limiting therun length of the same sign, and at least one cyclic coded bit for thecoded data sequence and at least one limit bit. Here, the redundant bitsmay include the above at least one limit bit on the more significant bitside and the above at least one cyclic coded bit on the less significantbit side. Alternatively, the redundant bits may include the above atleast one cyclic coded bit on the more significant bit side and theabove at least one limit bit on the less significant bit side. When16/17 modulation is used as digital modulation, it is necessary toprovide three bits for limit bits and 14 bits for cyclic coded bits.

[0080] Since the transmission characteristic of the reproducing systemis “1⊕D²” as the total transmission characteristic of the recording andreproducing system and the postcoder, a precoder 27 having atransmission characteristic of “1/(1⊕D²)” precodes the coded datasequence produced from the CRCC encoder 25.

[0081] The output data from the precoder 27 is supplied to arecording/reproducing circuit 20, where it is processed into a suitableform as a recording signal. The recording signal is recorded by magneticheads on a recording medium.

[0082] An embodiment of the data recording/reproducing apparatus of theinvention will be described with reference to related drawings.

[0083]FIG. 12 shows an example of hard disk drive (HDD) to which thepresent invention is applied. Referring to FIG. 12, an HDD 100 haschiefly a head disk assembly (HDA) 110 including magnetic disks 111,magnetic heads 112, a carriage 113, R/W ICs 114 mounted on the carriage,a spindle motor 115 and a flexible print cable (FPC) 116, and a printedcircuit board (PCB) 120 including a signal processing circuit (SPC) LSI121, a hard disk controller chip (HDC) 122, a servo controller (SRVC)123, a microprocessor (MP) 124, an SCSI (Small Computer SystemInterface) chip 125, a ROM 126 and a RAM 127. The CRCC 8 that makescoding and correction for short error correction is provided between theSPC 121 and HDC 122.

[0084] According to the invention, as described above, since the errorcaused at a high frequency by the maximum likelihood decoder 4 can becorrected by use of a simple CRCC just before the modulated codemodulator 10 and without breaking the 0-consecutive length limitationdue to the modulated code, the reliability of the recording channel canbe improved.

1. A signal processing apparatus comprising: a maximum likelihooddecoder for estimating a correct coded data sequence on the basis of aninput signal obtained from a digital signal transmission system fortransmitting a coded data sequence; a first error detection/correctioncircuit for detecting and correcting a predetermined error pattern of aplurality of error patterns generated in estimation operation of saidmaximum likelihood decoder; a code demodulator for demodulating thecoded data sequence output from said first error detection/correctioncircuit to obtain an information data sequence; and a second errordetection/correction circuit for detecting and correcting an error inthe information data sequence output from said code demodulator.
 2. Asignal processing apparatus according to claim 1, wherein said codeddata sequence is precoded for partial response, and said signalprocessing apparatus further comprising: a postcoder for postcoding thecoded data sequence output from said maximum likelihood decoder for apurpose of the partial response.
 3. A signal processing apparatusaccording to claim 1, wherein said first error detection/correctioncircuit detects and corrects the predetermined error pattern by use ofan error syndrome for at least one cyclic coded bit.
 4. A signalprocessing apparatus according to claim 1, wherein said first errordetection/correction circuit detects an error event occurrence by use oflikelihood information obtained from said maximum likelihood decoder,and selects to leave error alone or correct error depending on whetheror not a number of error events detected for each coded block is two ormore.
 5. A signal processing apparatus comprising: a first errorcorrection encoder for receiving an information data sequence, dividingsaid received information data sequence into data blocks, and addingerror correction codes to said data blocks; a digital modulation circuitfor digitally modulating said data blocks output from said first errorcorrection encoder so as to limit a run length of the same sign, thusgenerating a first number of data bits; and a second error correctionencoder for adding a second number of redundant bits including at leastone cyclic coded bit to said first number of data bits to successivelygenerate coded data blocks and outputting them as a coded data sequence.6. A signal processing apparatus according to claim 5, furthercomprising: a precoder for preceding the coded data sequence output fromsaid second error correction encoder for a purpose of partial response.7. A signal processing apparatus according to claim 5, wherein saidsecond number of redundant bits include at least one limit bit forlimiting a run length of the same sign and at least one cyclic coded bitfor said first number of data bits and said at least one limit bit.
 8. Asignal processing apparatus according to claim 7, wherein said secondnumber of redundant bits include said at least one limit bit on a moresignificant bit side and said at least one cyclic coded bit on a lesssignificant bit side.
 9. A signal processing apparatus according toclaim 7, wherein said second number of redundant bits include said atleast one cyclic coded bit on a more significant bit side and said atleast one limit bit on a less significant bit side.
 10. A datarecording/reproducing apparatus comprising: a first error correctionencoder for receiving an information data sequence, dividing saidreceived information data sequence into data blocks, and adding errorcorrection codes to said data blocks. a digital modulation circuit fordigitally modulating said data blocks output from said first errorcorrection encoder so as to limit a run length of the same sign, thusgenerating a first number of data bits; a second error correctionencoder for adding a second number of redundant bits including at leastone cyclic coded bit to said first number of data bits to successivelygenerate coded data blocks and outputting them as a coded data sequence;recording/reproducing means for recording a signal on a recording mediumon the basis of said coded data sequence, and reproducing the signalfrom said recording medium; a maximum likelihood decoder for estimatinga correct coded data sequence on the basis of said reproduced signal; afirst error detection/correction circuit for detecting and correcting apredetermined error pattern of a plurality of error patterns generatedin estimation operation of said maximum likelihood decoder; a codedemodulator for demodulating the coded data sequence output from saidfirst error detection/correction circuit to obtain an information datasequence; and a second error detection/correction circuit for detectingand correcting an error in the information data sequence output fromsaid code demodulator.
 11. A magnetic recording/reproducing apparatusaccording to claim 10, further comprising: a precoder for precoding thecoded data sequence output from said second error correction encoder fora purpose of partial response; and a postcoder for postcoding the codeddata sequence output from said maximum likelihood decoder for a purposeof the partial response.
 12. A signal processing method comprising thesteps of: (a) estimating a correct coded data sequence on the basis ofan input signal obtained from a digital signal transmission system fortransmitting a coded data sequence; (b) detecting and correcting apredetermined error pattern of a plurality of error patterns generatedin estimation operation at step (a); (c) demodulating the coded datasequence corrected at step (b) to obtain an information data sequence;and (d) detecting and correcting an error in the information datasequence obtained at step (c).
 13. A signal processing method accordingto claim 12, wherein said coded data sequence is precoded for partialresponse, and said method further comprising the step-of: postcoding thecoded data sequence estimated at step (a) for a purpose of the partialresponse.
 14. A signal processing method according to claim 12, whereinstep (b) includes detecting and correcting the predetermined errorpattern by use of an error syndrome for at least one cyclic coded bit.15. A signal processing method according to claim 12, wherein step (b)includes detecting an error event occurrence by use of likelihoodinformation obtained at step (a), and selecting to leave error alone orcorrect error depending on whether or not a number of error eventsdetected for each coded block is two or more.
 16. A signal processingmethod comprising the steps of: (a) receiving an information datasequence, dividing said received information data sequence into datablocks, and adding error correction codes to said data blocks; (b)digitally modulating said data blocks output at step (a) so as to limita run length of the same sign, thus generating a first number of databits; and (c) adding a second number of redundant bits including atleast one cyclic coded bit to said first number of data bits tosuccessively generate coded data blocks and outputting them as a codeddata sequence.
 17. A signal processing method according to claim 16,further comprising the step of: preceding the coded data sequence outputat step (c) for a purpose of partial response.
 18. A signal processingmethod according to claim 16, wherein said second number of redundantbits include at least one limit bit for limiting a run length of thesame sign and at least one cyclic coded bit for said first number ofdata bits and said at least one limit bit.
 19. A signal processingmethod according to claim 18, wherein said second number of redundantbits include said at least one limit bit on a more significant bit sideand said at least one cyclic coded bit on a less significant bit side.20. A signal processing method according to claim 18, wherein saidsecond number of redundant bits include said at least one cyclic codedbit on a more significant bit side and said at least one limit bit on aless significant bit side.